Lattice Semiconductor boosts automation and machine vision for Smart Factories
Lattice Semiconductor, a low-power programmable device and software stack provider, has updated its Lattice Automate and Lattice sensAI products. This company asserts that the recent upgrades will provide businesses with smart factory automation and AI-based machine vision advantages for industrial operations.
According to the company, Lattice Automate offers enterprise customers tools to evaluate, develop and deploy FPGA-based applications. The latest enhancements include support for implementing FreeRTOS RISC-V CPU on Certus Pro-NX FPGA. FreeRTOS is an open-source real-time operating system for microcontrollers and small embedded systems.
The company says this support allows developers to use the FPGA to run FreeRTOS on a RISC-V CPU, offering flexibility in embedded application creation.
Lattice Automate has also expanded its design tools by integrating the FreeRTOS OPC-UA (open platform communications- unified architecture). The company says that combining these two technologies provides a complete solution for developing IoT and industrial automation applications. Further, the FreeRTOS OPC-UA secures the communication between multiple IoT-connected devices across a network.
The Lattice sensAI software stack supports the development of FPGA-based ML-embedded applications that rely on minimal power usage. It is also specifically designed for applications that require on-device AI capability at the edge, such as smart cities and factory automation.
Additionally, the Lattice sensAI witnessed an upgrade in its accelerator engine. It can now support OpenCV and standard machine learning platforms. The accelerator engine speeds up processing tasks for video analytics and image recognition.
With the support of OpenCV, an open-source computer vision library, customers can perform image and video analytics tasks more accurately, company executives say.
Article Topics
chip | computer vision | edge AI | FPGA | Industry 4.0 | Lattice Semiconductor | RISC-V
Comments