Imperas boosts its RISC-V model library with Tenstorrent Ascalon processor
Imperas Software, a RISC-V simulation solutions provider, has partnered with Tenstorrent, a provider of embedded hardware tailored for artificial intelligence applications, to offer system-on-chip developers a virtual model of the Ascalon RISC-V processor core.
This virtual model allows them to efficiently assess, develop, and test their designs before physical manufacturing takes place. In the early stages of evaluation and testing, a functional representation through software simulation provides SoC developers with the ability to interact with the processor as if it were actual hardware.
Imperas highlights the importance of high-quality reference models that represent the configurability of the processor’s IP core for virtual platforms in system SoC projects. With Imperas’ RISC-V model library, geographically dispersed teams can collaborate remotely through these virtual platforms.
“The Tenstorrent Ascalon processor is focused on serving the compute requirements of next-generation workloads emerging at the edge and data center/cloud with the rapid proliferation of AI high-performance applications, including edge AI and HPC,” says Aniket Saha, vice president of product strategy at Tenstorrent.
Imperas states that the Ascalon processor model is compatible with standard Electronic Design Automation (EDA) environments and can integrate with languages such as SystemC and SystemVerilog. Additionally, it is compatible with simulation tools offered by companies like Cadence, Siemens EDA, and Synopsys.
Imperas also emphasizes a hybrid approach that combines Imperas’ simulation technology with emulation environments, allowing for complex designs. In this approach, Imperas models can serve the purpose of meeting interim analysis requirements, even while some parts of the Register-Transfer Level (RTL) of the System-on-Chip (SoC) are still in the development phase.
“Now developers using the Tenstorrent Ascalon IP can use the Imperas models as a reference for software development to support the shift-left of project schedules,” adds Simon Davidmann, chief executive officer at Imperas Software Limited.
Imperas has developed the Open Virtual Platform (OVP), a no-cost simulation software consisting of three primary components – OVP APIs that facilitate the creation of C models, a library of open-source processor and peripheral models, and OVPsim, a simulator capable of executing these models.
Article Topics
Imperas | RISC-V | SoC | software | Tenstorrent
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